Targeted, preconfigured RISC-V IP cores plus low-risk, easy-start, deferred-payment IP licensing make embedded RISC-V design easier than ever Santa Clara, California, RISC-V Summit — October 22, 2025 ...

CAST, the semiconductor intellectual property provider, has unveiled the CAST Catalyst Program. This program is a new way for embedded system developers to adopt RISC-V processors faster and with less ...

BANGKOK, Dec. 12, 2019 /PRNewswire/ -- RISC-V Summit -- The trend towards compute intensive gateways and edge devices is driving the integration of traditional deterministic control applications with ...

It’s pretty neat to flash firmware on a microcontroller thousands of miles away and see the development board blink in response. We’ve covered the Open-V before, and the crowd funding campaign they ...

This blog will look at recent developments in RISC-V and in particular at announcements by Western Digital at the 2018 RISC-V Summit in Santa Clara, CA. RISC-V is an open, scalable instruction set ...

June 8, 2021 Nicole Hemsoth Prickett Compute Comments Off on AI Is RISC-V’s Trojan Horse into the Datacenter If the workload-specific datacenter dominates in the near term, it could be RISC-V’s time ...

The third annual RISC-V summit takes place next month, 8-10 December 2020, and like the majority of events this year, will be completely online. The program features three days of talks around ...

IP that’s built on a RISC-V vector processing CPU. The platform has been augmented to support artificial-intelligence/machine ...

If you wanted to make a CPU, and you’re not AMD or Intel, there are two real choices: ARM and RISC-V. But what are the differences between the two, and why do companies choose one over the other?

A computer processor uses a so-called Instruction Set Architecture to talk with the world outside of its own circuitry. This ISA consists of a number of instructions, which essentially define the ...