IEEE

Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA

Abstract: This paper presents an automated RegisterTransfer Level (RTL) code generator for energy-efficient oddeven merge sorting networks, optimizing hardware complexity for FPGA-based ...
IEEE

Non-dominated Sorting Genetic Algorithm Optimization Design of a Compact Broadband ...

Abstract: This paper proposes a mode converter design based on an asymmetric dual hollow core antiresonant fiber (ADHCARF), which is applicable to high-capacity mode-division multiplexing (MDM) ...